1. Field of the Invention
The invention relates to testing of semiconductor devices, and more particularly to selectable power supply lines for use in isolating defects in integrated circuits.
2. Description of the Related Art
Integrated circuits (ICs) have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can often be reduced to a single integrated circuit. These integrated circuits (also referred to as "chips") may use many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, mixed signal and analog functions, communication circuitry, and large blocks of memory and high speed interfaces. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, the complex nature of today's integrated circuits presents new testing challenges. Continually shrinking device geometries, coupled with the high cost of operating semiconductor processing equipment, result in increased demands on integrated circuit suppliers to improve process yields through developing new test strategies.
Currently, complementary metal-oxide-semiconductor (CMOS) is the most popular technology for fabricating integrated circuits due to its inherent low power consumption in high density designs. CMOS circuits use complementary p-channel metal-oxide-semiconductor field-effect (PMOS) transistors and n-channel metal-oxide-semiconductor field-effect (NMOS) transistors to produce fully static designs that ideally consume no power except when switching states. In practice, however, CMOS circuits consume low leakage or quiescent currents--also referred to as quiescent power supply current or IDDQ--in a static state.
If an integrated circuit should fail, in many cases unusual current levels can be detected, typically in the form of excessive amounts of quiescent current The excessive amounts of quiescent current occur when a manufacturing defect causes the integrated circuit to be ill-conditioned to quiescent current test states.
Many general test development strategies for integrated circuits have evolved, and often combinations of these strategies are utilized to provide a high degree of fault coverage. Test development strategies include functional test wherein automatic test equipment (ATE) test programs are performed in which the circuit under test is stimulated with specified inputs while the outputs are monitored to determine if they correspond with simulated logic values.
Another test development strategy, physical defect testing, involves creating specific tests designed to detect possible real physical defects that can occur in a circuit. Physical testing is useful for detecting defects that may not cause the device to fail functional or structural testing, but may lead to failure in the field. Defects in integrated circuits take many forms, some of which are test pattern sensitive. Gate oxide defects, drain to source current leaks (punch-through), and p-n junction current leaks (such as drain or source to diffusion current leaks) tend to be pattern sensitive, while resistive shorts to ground or the power supply voltage are usually pattern insensitive. In either case, quiescent current tests are a valuable tool in detecting faults.
Generally, the result of test development is an ATE test program or test "set" providing stimulus/response test "vectors" in the language of the ATE. The ATE test set causes the inputs of the device under test to be driven in a predetermined manner, while output pin voltages are compared to stored test values. The ATE test set is derived mainly from functional and structural test development logic simulations.
When testing quiescent current with a functional test set, the tester is generally halted at predetermined test steps suitable for quiescent current testing. Once halted (i.e., no transistor state switching is occurring) the power supply of the device under test is measured by the ATE and the resulting value is compared to predetermined reference values or test limits. Such quiescent current tests are effective in detecting many faults that would otherwise not be found by other test strategies.
For example, with most functional tests that measure voltage, faults must propagate to the output pins of the device under test for the ATE to differentiate between a good or bad device. Quiescent current tests differ in that current is sensed rather than voltage, providing a simple means to monitor the entire circuit or portions thereof for over-current conditions. The quiescent current measurements are typically accomplished via the tester's parametric unit.
Accurate quiescent current testing requires that the device under test be in a static DC condition, with any circuitry that consumes current in the static DC condition being disabled or accounted for in the test limits. Preferably analog circuitry, input/output pads, and other circuitry not conducive to quiescent current testing are provided with separate, dedicated power supply inputs, so that digital core circuitry can be tested separately.
In order to isolate the defective area of an integrated circuit, a failure analysis engineer seeks to determine which section of the integrated circuit is responsible for unusual current levels. Quiescent current testing to detect which section of an integrated circuit includes a defect, however, has been complicated by current distributed within other sections of the integrated circuit, particularly sections in the same region of the integrated circuit. One known approach to this problem has been the procedure of cutting lines and/or depositing additional metal for "jumpering" lines to condition the desired section of an integrated circuit for a quiescent mode. This approach has typically included measuring current in a region of the integrated circuit, cutting lines to sections within the same region other than the section of interest, and then taking a additional measurements of current in the region.
Such failure analysis techniques have not adequately localized defects in particular regions of an integrated circuit. Certain sections of an integrated circuit, such as sections in the same region of an integrated circuit, often share common (or unitary) power supply lines. It has been difficult to isolate a particular section having a defect from other sections in the same region of the integrated circuit which share power supply lines.
Other related failure analysis approaches include photon emission microscopy, E-beam testing, backside infrared imaging, and optical beam induced current techniques. Photon emission microscopy typically involves use of an emission microscope sensitive to electron-hole recombination. When an electron hole recombination occurs, some of the excess energy is given off as photon emission. Photon emission microscopy is primarily effective for detection of a unique subset of leakage type failures and semiconductor overstress conditions. In E-beam testing, a variety of voltage characterization techniques (such as state voltage contrast, dynamic fault imaging, and electron beam involved current) in conjunction with functional stimulus are used to collect data for locating physical defects.
With backside infrared imaging, the backside of a die is exposed to infrared emissions to induce current. A laser scanning microscope is then used to observe those areas of the die of relatively high heat dissipation which will reflect infrared energy. In optical beam induced current techniques, a laser is used to scan energy across a sample to generate electron-hole pairs. The electron-hole pairs become swept up by the voltage across the space-charge regions in the sample. The resulting current is amplified to generate an image. The current-generated image may be superimposed on the reflected light image to correlate the current to a physical location which is often associated with a defective site. Many of these testing techniques, however, are time consuming and cannot be utilized in conjunction with ATE test programs.